Job description
Role -Senior Design Verification Engineer
Location -San Jose, CA –day 1 onsite
Type -Full Time only
Job Description
- SV UVM – Subsystem and Full chip level.
- SOC / subsystem/ IP /module level verifications from spec to silicon bring up
- Experience of working closely with backend team for timing closure
- Experience with constrained, random, C based Processor, GLS, Low power, Assertions based verifications.
- Custom Clocking experience, understanding Database
- Good Working knowledge on standard protocols/modules, Power Domains, Clock Gating,
- LPF/UPFs based verifications.
- Good in shell scripting, perl scripting.
- Cadence and Synopsys experience
Job Type: Full-time
Salary: $65,590.27 - $120,000.00 per year
Experience level:
- 10 years
- 11+ years
- 8 years
- 9 years
Ability to commute/relocate:
- San Jose, CA: Reliably commute or planning to relocate before starting work (Required)
Willingness to travel:
- 25% (Preferred)
Work Location: One location
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