Job description
At Cyient's Semiconductor, IoT, and Analytics (SI&A) business unit, we are proud to work on technology that is transforming how ordinary things work to perform better and provide greater convenience.
Cyient brings more than 20 years of experience in semiconductor and software systems solutions and services. Our strong technical and domain expertise with a robust ecosystem partnership makes us your trusted global semiconductor partner, from concept to production.
With the integration of two key acquired technologies, semiconductor, and digital transformation, into our services, we offer the Industrial Internet of Things (IIoT) industry end-to-end digital solutions. We support embedded intelligence at the edge, connected intelligence in the cloud, and actionable intelligence for the customer.
Job Description
About the Role:
- You will help build detailed transistor-level layout of RF and Analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, base band filters, and band gap/bias/LDO. Block level and top-level layout through full verification flow including extraction, DRC, LVS,and DFM checking Co-work with designers on block level and top-level floor-planning Layout review for power/gnd routing, electro-migration, signal path check, differential and IQ matching, and signal coupling.
- Experience in custom RF/Analog layout with knowledge of deep sub-micron CMOS (40nm, 28nm, FinFet.
- You will have a minimum experience of 10 -15 yrs.
- You will work in the Munich as a RFIC Layout Senior Engineer.
- You will report directly to the Delivery Head - Semiconductor based in India.
You Will:
- You will need experience in custom RF/Analog layout with knowledge of deep sub-micron CMOS (40nm, 28nm, FinFet.)
- You will need to be Knowledgeable in layout techniques for device matching, minimising parasitics, RF shielding, and high frequency routing Must have experience in 7nm or less
- You will help build detailed transistor-level layout of RF and Analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/ DAC, base band filters, and band gap/bias/LDO. Block level and top-level layout through full verification flow including extraction, DRC, LVS, and DFM checking Co-work with designers on block level and top-level floor-planning Layout review for power/gnd routing, electro-migration, signal path check, differential and IQ matching, and signal coupling.
You'll Need:
- You will need Experience with RC delay, electro migration, and coupling Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE.
- You will need to have High-level proficiency in interpretation of CALIBRE DRC, ERC, LVS, and Knowledge of Schedule layout tools.
Skills & Experience
Cadence Virtuoso, Custom Layout Design, Radio-Frequency Integrated Circuit (RFIC)
Cyient is an Equal Opportunity Employer.
Cyient recruits, employs, trains, compensates, and promotes regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender, gender identity or expression, veteran status, and other protected status as required by applicable law. We are proud to be a diverse and inclusive company where our people can focus their whole self on solving problems that matter.
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